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Bitmask for hstatus

I'm trying to come up with the legal read/write bitmask for hstatus. In the five-embedded hypervisor extension i see this image. You may have to open in new image, it's showing poorly in this editor view.

https://preview.redd.it/j0iqa12zej2f1.png?width=1340&format=png&auto=webp&s=e77c1f08a6a4668fdebdb2a9849f4939b8cb825e

0 - 4 is 0
so this is 5 bits of 0,
VSBE states it's length is 2 indicated by the bottom. All of them seem this way to accurately represent the number except VSBE and SPVP.

Do I need to assume that if its length is two, but the indicated register is only one bit in length. it is paired into the left indicated field? (SPV and SPVP) make sense to be together but that is to the right field, which would mean VSBE pairs with the wpri field?

https://redd.it/1ktpcvt
@r_riscv

www.tg-me.com/us/RISC V Reddit/com.r_riscv/3348

9 viewsMay 23 at 18:24

Bitmask for hstatus

I'm trying to come up with the legal read/write bitmask for hstatus. In the five-embedded hypervisor extension i see this image. You may have to open in new image, it's showing poorly in this editor view.

https://preview.redd.it/j0iqa12zej2f1.png?width=1340&format=png&auto=webp&s=e77c1f08a6a4668fdebdb2a9849f4939b8cb825e

0 - 4 is 0
so this is 5 bits of 0,
VSBE states it's length is 2 indicated by the bottom. All of them seem this way to accurately represent the number except VSBE and SPVP.

Do I need to assume that if its length is two, but the indicated register is only one bit in length. it is paired into the left indicated field? (SPV and SPVP) make sense to be together but that is to the right field, which would mean VSBE pairs with the wpri field?

https://redd.it/1ktpcvt
@r_riscv

BY RISC-V Reddit